R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 461

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.6.2
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize
the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer
format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When
the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not
initialize the RDRF, PER, FER, and ORER flags, or RDR.
SCI Initialization (Clocked Synchronous Mode)
Note: In simultaneous transmit and receive operations, the TE and RE bits should both
Clear TE and RE bits in SCR to 0
Set TE or RE bit in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
Set corresponding bit in ICR to 1
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
be cleared to 0 or set to 1 simultaneously.
(TE and RE bits are 0)
1-bit interval elapsed?
Start initialization
Set value in BRR
SMR and SCMR
<Transfer start>
Figure 12.15 Sample SCI Initialization Flowchart
Yes
Wait
No
[2]
[3]
[5]
[1]
[4]
[1]
[2] Set the clock selection in SCR. Be sure
[3] Set the data transfer format in SMR and
[4] Write a value corresponding to the bit
[5] Wait at least one bit interval, then set
to clear bits RIE, TIE, TEIE, and MPIE,
and bits TE and RE, to 0.
SCMR.
rate to BRR. This step is not necessary
if an external clock is used.
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits. Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Section 12 Serial Communication Interface (SCI)
Set the bit in ICR for the corresponding
pin when receiving data or using an
external clock.
Rev. 3.00 Mar. 14, 2006 Page 423 of 804
REJ09B0104-0300