R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 445

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the
basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception
margin in asynchronous mode is determined by formula (1) below.
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 –
M: Reception margin
N: Ratio of bit rate to clock (N = 16)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
M = ( 0.5 –
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
|
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
2 × 16
2N
1
1
0
) – (L – 0.5) F –
) × 100
8 clocks
Start bit
16 clocks
[%] = 46.875%
7
| D – 0.5 |
N
(1
15 0
F ) | × 100
Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 407 of 804
D0
[%]
... Formula (1)
7
REJ09B0104-0300
15 0
D1