R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 173

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

A block diagram of the DMAC is shown in figure 7.1.
Internal activation sources
Internal activation
source detector
Note: * Auto request activation and single address mode are not supported by the
[Legend]
DSAR_n: DMA source address register
DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge
DOFR_n: DMA offset register
DTCR_n: DMA transfer count register
DBSR_n: DMA block size register
DMDR_n: DMA mode control register
DACR_n: DMA address control register
DMRSR_n:
Interrupt signals
requested to the
CPU by each
channel
DMRSR_n
...
External pins
DREQn*
DACKn*
TENDn*
H8SX/1520 Group.
Figure 7.1 Block Diagram of DMAC
Controller
DMDR_n
DACR_n
Module data bus
Internal address bus
DMA module request select register
DREQn: DMA transfer request
TENDn: DMA transfer end
n = 0 to 3
Address buffer
Operation unit
Operation unit
DOFR_n
DDAR_n
DBSR_n
DSAR_n
DTCR_n
Rev. 3.00 Mar. 14, 2006 Page 135 of 804
Section 7 DMA Controller (DMAC)
Internal data bus
Data buffer
REJ09B0104-0300