R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 329

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Bit
3
2
1
0
*
Bit Name
TGIED
TGIEC
TGIEB
TGIEA
Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should
always be 0.
0
0
0
0
Initial
value
R/W
R/W
R/W
R/W
R/W
Description
TGR Interrupt Enable D
Enables/disables interrupt requests (TGID) by the TGFD
bit when the TGFD bit in TSR is set to 1 in channels 0
and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is a read-
only bit and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
TGR Interrupt Enable C
Enables/disables interrupt requests (TGIC) by the TGFC
bit when the TGFC bit in TSR is set to 1 in channels 0
and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is a read-
only bit and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
TGR Interrupt Enable B
Enables/disables interrupt requests (TGIB) by the TGFB
bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable A
Enables/disables interrupt requests (TGIA) by the TGFA
bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 3.00 Mar. 14, 2006 Page 291 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
REJ09B0104-0300