R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 304

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.5
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Table 9.6
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Rev. 3.00 Mar. 14, 2006 Page 266 of 804
REJ09B0104-0300
Channel
0, 3
Channel
1, 2, 4, 5
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is a read-only bit and cannot be modified.
buffer register setting has priority, and compare match/input capture does not occur.
Bit 7
CCLR2
0
0
0
0
1
1
1
1
Bit 7*
Reserved
0
0
0
0
CCLR2 to CCLR0 (Channels 0 and 3)
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
2
Bit 6
CCLR1
0
1
0
0
1
1
Bit 6
CCLR1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture*
TCNT cleared by TGRD compare match/input
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
2
2
1
1
1