R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 221

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.10
(1)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one
word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus
released cycles.
In figure 7.24, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by cycle stealing.
In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords
from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal
transfer mode by cycle stealing.
In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the
transfer destination (DDAR) is aligned with a longword boundary.
In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer
destination (DDAR) is not aligned with a longword boundary.
B
Address bus
RD
LHWR, LLWR
TEND
Normal Transfer Mode (Cycle Stealing Mode)
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
Bus
released
Bus Cycles in Dual Address Mode
DMA read
cycle
DMA write
cycle
Bus
released
DMA read
cycle
DMA write
cycle
Rev. 3.00 Mar. 14, 2006 Page 183 of 804
Bus
released
Section 7 DMA Controller (DMAC)
DMA read
cycle
Last transfer cycle
REJ09B0104-0300
DMA write
cycle
Bus
released