R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 102

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.9
The H8SX CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and program stop state. Figure 2.16 indicates the state
transitions.
• Reset state
• Exception-handling state
• Program execution state
• Bus-released state
• Program stop state
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In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. The reset state can also be entered by a watchdog timer overflow.
For details, refer to section 4, Exception Handling.
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or
trap instruction. The CPU fetches a start address (vector) from the exception handling vector
table and branches to that address. For further details, refer to section 4, Exception Handling.
In this state the CPU executes program instructions in sequence.
In this state, the bus has been released in response to a bus request from the DMA controller
(DMAC). While the bus is released, the CPU halts operations.
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters software standby mode. For details,
refer to section 19, Power-Down Modes.
Processing States