R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 379

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.9.9
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 9.52 shows the timing in this case.
9.9.10
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 9.53 shows the timing in this case.
Conflict between TGR Write and Input Capture
Conflict between Buffer Register Write and Input Capture
Figure 9.53 Conflict between Buffer Register Write and Input Capture
P
Address
Write
Input capture
signal
TCNT
TGR
P
Address
Write
Input capture
signal
TCNT
TGR
Buffer register
Figure 9.52 Conflict between TGR Write and Input Capture
Buffer register write cycle
TGR write cycle
M
TGR address
T1
Buffer register
T1
address
N
T2
T2
M
M
Rev. 3.00 Mar. 14, 2006 Page 341 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
N
M
REJ09B0104-0300