R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 240

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar. 14, 2006 Page 202 of 804
REJ09B0104-0300
DMAC is activated in
transfer size error state
DMAC is activated
after BKSZ bits are
changed from 1 to 0
Extended repeat area
overflow occurs in
source address
Extended repeat area
overflow occurs in
destination address
Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.
DARIE bit
SARIE bit
RPTIE bit
ESIF bit in DMDR to 0 and an interrupt source is cleared.
TSIE bit
Interrupt handling routine
Registers are specified
ends (RTE instruction
Transfer end interrupt
Consecutive transfer
DTE bit is set to 1
Transfer resume
handling routine
processing end
processing
executed)
Figure 7.38 Interrupt and Interrupt Sources
[1]
[2]
[3]
Interrupt handling routine
interrupt handling routine
DTIF and ESIF bits are
Transfer resumed after
Registers are specified
DTE bit is set to 1
Transfer resume
processing end
DTIE bit
Setting condition is satisfied
DTIF bit
ESIE bit
ESIF bit
cleared to 0
ends
[Setting condition]
When DTCR becomes 0
and transfer ends
[6]
[4]
[5]
[7]
Transfer end
interrupt
Transfer escape
end interrupt