R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 723

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.8
Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for
the corresponding PA7 pin.
Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When
bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock
output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and
the pin becomes an input port.
Disabling Bφ output can reduce electromagnetic interference (EMI). Take it into consideration for
design of the user system board.
Tables 19.3 shows the states of the Bφ pin in each processing state.
Table 19.3 Bφ Pin (PA7) State in Each Processing State
DDR
0
1
1
1
Register Setting Value
Bφ Clock Output Control
PSTOP1
X
0
0
1
POSEL1
X
0
1
X
Normal
Operating
State
Hi-Z
Bφ output
Setting
prohibited
High
Sleep Mode
Hi-Z
Bφ output
Setting
prohibited
High
Rev. 3.00 Mar. 14, 2006 Page 685 of 804
All-Module-
Clock-Stop
Mode
Hi-Z
Bφ output
Setting
prohibited
High
Section 19 Power-Down Modes
OPE = 0
Hi-Z
High
Setting
prohibited
High
Software Standby Mode
REJ09B0104-0300
OPE = 1
Hi-Z
High
Setting
prohibited
High