R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 825

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
14.3.7 SS Transmit Data
Registers 0 to 3 (SSTDR0 to
SSTDR3)
Table 14.2 Correspondence
Between DATS Bit Setting and
SSTDR
14.3.8 SS Receive Data Registers
0 to 3 (SSRDR0 to SSRDR3)
Table 14.3 Correspondence
Between DATS Bit Setting and
SSRDR
14.4.5 SSU Mode
Figure 14.4 Example of Initial
Settings in SSU Mode
Figure 14.6 Flowchart Example of
Data Transmission (SSU Mode)
Figure 14.8 Flowchart Example of
Data Reception (SSU Mode)
523
524
524
525
530
533
536
Page Revision (See Manual for Details)
Added
Be sure not to access invalid SSTDRs.
Added
Added
Be sure not to access invalid SSRDRs
Added
Amended
Deleted
Deleted
[4]
[5]
[1]
[2]
[1]
[2]
and CEIE bits in SSER simultaneously
Specify MLS, CPOS, CPHS, CKS2,
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS and SSODTS
TE = 1 (transmission enabled)
Rev. 3.00 Mar. 14, 2006 Page 787 of 804
Specify TE, RE, TEIE, TIE, RIE,
CKS1, and CKS0 bits in SSMR
RE = 1 (receprion started)
Start setting initial values
Read TDRE in SSSR
Dummy-read SRDR
Initial setting
Initial setting
bits in SSCR2
Start
Start
End
REJ09B0104-0300