R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 336

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.9
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Rev. 3.00 Mar. 14, 2006 Page 298 of 804
REJ09B0104-0300
Bit
7, 6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name

SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Timer Synchronous Register (TSYR)
R/W
—
7
0
Initial
value
All 0
0
0
0
0
0
0
R/W
—
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYNC5
R/W
5
0
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent of or
synchronized with other channels.
When synchronous operation is selected, synchronous
presetting of multiple channels, and synchronous clearing
through counter clearing on another channel are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to
CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operate independently (TCNT
1: TCNT_5 to TCNT_0 perform synchronous operation
Description
presetting/clearing is unrelated to other channels)
(TCNT synchronous presetting/synchronous clearing
is possible)
SYNC4
R/W
4
0
SYNC3
R/W
3
0
SYNC2
R/W
2
0
SYNC1
R/W
1
0
SYNC0
R/W
0
0