R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 504

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 466 of 804
REJ09B0104-0300
Bit
14
13
12
Bit Name
IRR6
IRR5
IRR4
Initial
Value
0
0
0
R/W
R/(W)*
R/(W)*
R/(W)*
Description
Bus Off Interrupt Flag
Status flag indicating the bus off state caused by
the transmit error counter.
[Setting condition]
When TEC ≥ 256
[Clearing condition]
Writing 1
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
Error Passive Interrupt Flag
Status flag indicating the error passive state
caused by the transmit/receive error counter.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
Writing 1
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
Receive Overload Warning Interrupt Flag
Status flag indicating the error warning state
caused by the receive error counter.
[Setting condition]
When REC ≥ 96
[Clearing condition]
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
Writing 1

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