R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 12

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC) ........................................................................ 125
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Section 7 DMA Controller (DMAC)................................................................. 133
7.1
7.2
7.3
7.4
Rev. 3.00 Mar. 14, 2006 Page xii of xxxviii
Features.............................................................................................................................. 125
Register Descriptions......................................................................................................... 126
6.2.1
Bus Configuration.............................................................................................................. 127
Multi-Clock Function ........................................................................................................ 128
Internal Bus........................................................................................................................ 129
6.5.1
Write Data Buffer Function ............................................................................................... 130
6.6.1
Bus Arbitration .................................................................................................................. 131
6.7.1
6.7.2
Bus Controller Operation in Reset ..................................................................................... 132
Usage Notes ....................................................................................................................... 132
Features.............................................................................................................................. 133
Register Descriptions......................................................................................................... 136
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Transfer Modes .................................................................................................................. 157
Operations.......................................................................................................................... 158
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 Bus Cycles in Dual Address Mode ....................................................................... 183
Bus Control Register 2 (BCR2) ............................................................................ 126
Access to Internal Address Space ......................................................................... 129
Write Data Buffer Function for Peripheral Module ............................................... 130
Operation .............................................................................................................. 131
Bus Transfer Timing............................................................................................. 131
DMA Source Address Register (DSAR) .............................................................. 137
DMA Destination Address Register (DDAR) ...................................................... 138
DMA Offset Register (DOFR).............................................................................. 139
DMA Transfer Count Register (DTCR) ............................................................... 140
DMA Block Size Register (DBSR) ...................................................................... 141
DMA Mode Control Register (DMDR)................................................................ 142
DMA Address Control Register (DACR)............................................................. 151
DMA Module Request Select Register (DMRSR) ............................................... 157
Address Modes ..................................................................................................... 158
Transfer Modes..................................................................................................... 162
Activation Sources................................................................................................ 166
Bus Access Modes................................................................................................ 168
Extended Repeat Area Function ........................................................................... 170
Address Update Function using Offset ................................................................. 172
Register during DMA Transfer............................................................................. 176
Priority of Channels.............................................................................................. 181
DMA Basic Bus Cycle.......................................................................................... 182