R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 120

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Exception Handling
4.6.2
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiple-interrupt control. The source to start interrupt exception handling and the vector address
differ depending on the product. For details, refer to section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the interrupt source is generated,
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the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Interrupt Exception Handling