R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 447

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.4.4
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize
the SCI as described in a sample flowchart in figure 12.5. When the operating mode, transfer
format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When
the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
SCI Initialization (Asynchronous Mode)
Clear TE and RE bits in SCR to 0
SCR to 1, and set RIE, TIE, TEIE,
Set corresponding bit in ICR to 1
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
<Initialization completion>
(TE and RE bits are 0)
1-bit interval elapsed
Set TE or RE bit in
Start initialization
Set value in BRR
SMR and SCMR
and MPIE bits
Figure 12.5 Sample SCI Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Section 12 Serial Communication Interface (SCI)
Set the bit in ICR for the corresponding
pin when receiving data or using an
external clock.
Set the clock selection in SCR.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, the clock is output
immediately after SCR settings are
made.
Set the data transfer format in SMR and
SCMR.
Write a value corresponding to the bit
rate to BRR. This step is not necessary
if an external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1. Also set
the RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Rev. 3.00 Mar. 14, 2006 Page 409 of 804
REJ09B0104-0300