R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 523

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(1)
The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software
standby mode. Since an HCAN interrupt is initiated immediately when interrupts are enabled,
IRR0 should be cleared.
IRR0 Clearing
Message transmission method initialization
LAFM setting (receive identifier mask setting)
MC[x] setting (receive identifier setting)
MBIMR setting (interrupt mask setting)
IMR setting (interrupt mask setting)
Can bus communication enabled
Initialization of HCAN module
recessive bits received?
MCR0 = 1 (automatic)
GSR3 = 1 (automatic)
IRR0 = 1 (automatic)
Mailbox initialization
Hardware reset
GSR3 = 0 & 11
MBCR setting
GSR3 = 0?
BCR setting
Clear IRR0
MCR0 = 0
Yes
Yes
Figure 13.6 Hardware Reset Flowchart
No
No
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 485 of 804
: Settings by user
: Processing by hardware
REJ09B0104-0300