R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 233

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(5)
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is
delayed for one cycle.
Figure 7.37 shows an example of single address mode activated by the DREQ signal low level
with NRD = 1.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after one cycle of the transfer
request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the
DREQ signal is detected. This operation is repeated until the transfer is completed.
B
DREQ
Address bus
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed one cycle after completion of the single cycle.
Activation Timing by DREQ Low Level with NRD = 1
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 7.37 Example of Transfer in Single Address Mode Activated
[1]
Request
released
Bus
Min. of 3 cycles
[2]
Duration of transfer
request disabled
by DREQ Low Level with NRD = 1
[3]
Transfer destination
DMA single
Transfer source/
cycle
Duration of transfer request
disabled which is extended
Transfer request
enable resumed
by NRD
[4]
Request
Min. of 3 cycles
released
[5]
Bus
Rev. 3.00 Mar. 14, 2006 Page 195 of 804
Duration of transfer
request disabled
[6]
Transfer destination
Section 7 DMA Controller (DMAC)
DMA single
Transfer source/
cycle
Duration of transfer request
disabled which is extended
Transfer request
enable resumed
by NRD
released
Bus
[7]
REJ09B0104-0300