R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 364

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9 16-Bit Timer Pulse Unit (TPU)
9.5
There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priority levels can be changed by the interrupt controller, but the priority within a
channel is fixed. For details, see section 5, Interrupt Controller.
Table 9.39 lists the TPU interrupt sources.
Table 9.39 TPU Interrupts
Rev. 3.00 Mar. 14, 2006 Page 326 of 804
REJ09B0104-0300
Channel Name
0
1
2
Interrupt Sources
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
Interrupt Source
TGRA_0 input capture/compare match
TGRB_0 input capture/compare match
TGRC_0 input capture/compare match
TGRD_0 input capture/compare match
TCNT_0 overflow
TGRA_1 input capture/compare match
TGRB_1 input capture/compare match
TCNT_1 overflow
TCNT_1 underflow
TGRA_2 input capture/compare match
TGRB_2 input capture/compare match
TCNT_2 overflow
TCNT_2 underflow
Interrupt Flag
TGFA_0
TGFB_0
TGFC_0
TGFD_0
TCFV_0
TGFA_1
TGFB_1
TCFV_1
TCFU_1
TGFA_2
TGFB_2
TCFV_2
TCFU_2
Possible
Possible
Possible
DMAC
Activation
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible

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