R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 122

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Exception Handling
4.7.2
There are two illegal instructions: general illegal instruction and slot illegal instruction.
The exception handling by the general illegal instruction starts when an undefined code is
decoded.
The exception handling by the slot illegal instruction starts when the following instruction which
is placed in a delay slot (immediately after a delayed branch instruction) is executed: an
instruction which consists of two words or more or which changes the contents of PC.
The general illegal and slot illegal instructions are always executable in the program execution
state.
The exception handling for the general illegal and a slot illegal instructions is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the occurred exception is
Table 4.9 shows the state of CCR and EXR after execution of illegal instruction exception
handling.
Table 4.9
[Legend]
1:
0:
:
Rev. 3.00 Mar. 14, 2006 Page 84 of 804
REJ09B0104-0300
Interrupt Control Mode
0
2
generated, the start address of the exception service routine is loaded from the vector table to
PC, and program execution starts from that address.
Set to 1
Cleared to 0
Retains the previous value.
Exception Handling by Illegal Instruction
Status of CCR and EXR after Illegal Instruction Exception Handling
I
1
1
CCR
UI


T

0
EXR
I2 to I0

