MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 999

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

41.3.3 Control 1 Register (CANx_CTRL1)
This register is defined for specific FlexCAN control features related to the CAN bus,
such as bit-rate, programmable sampling point within an Rx bit, Loop Back Mode,
Listen-Only Mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error,
Warning). It also determines the Division Factor for the clock prescaler.
Addresses: CAN0_CTRL1 is 4002_4000h base + 4h offset = 4002_4004h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
PRESDIV
W
W
R
R
PSEG1
PSEG2
31–24
23–22
21–19
18–16
RJW
Field
31
15
0
0
30
14
0
0
Prescaler Division Factor
This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency.
The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock
frequency is equal to the PE clock frequency. The Maximum value of this field is 0xFF, that gives a
minimum Sclock frequency equal to the PE clock frequency divided by 256. See Section "Protocol
Timing". This field can only be written in Freeze mode as it is blocked by hardware in other modes.
Sclock frequency = PE clock frequency / (PRESDIV + 1)
Resync Jump Width
This 2-bit field defines the maximum number of time quanta that a bit time can be changed by one re-
synchronization. (One time quantum is equal to the Sclock period.) The valid programmable values are 0–
3. This field can only be written in Freeze mode as it is blocked by hardware in other modes.
Resync Jump Width = RJW + 1.
Phase Segment 1
This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time. The valid programmable
values are 0–7. This field can only be written in Freeze mode as it is blocked by hardware in other modes.
Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta.
Phase Segment 2
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable
values are 1–7. This field can only be written in Freeze mode as it is blocked by hardware in other modes.
29
13
0
0
LPB
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
PRESDIV
28
12
0
0
27
11
0
0
CANx_CTRL1 field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
0
24
0
0
8
Description
SMP
23
0
0
7
RJW
22
0
0
6
21
0
0
5
PSEG1
20
0
0
4
Chapter 41 CAN (FlexCAN)
19
0
0
3
18
0
0
2
PROPSEG
PSEG2
17
0
0
1
16
0
0
0
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