MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 952

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
39.6.6 CMT Modulator Status and Control Register (CMT_MSC)
The MSC register contains the modulator and carrier generator enable (MCGEN), end of
cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable (BASE),
extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status
bit.
Address: CMT_MSC is 4006_2000h base + 5h offset = 4006_2005h
952
CMTDIV
EXSPC
EOCF
Reset
Field
Read
6–5
Write
7
4
Bit
EOCF
End Of Cycle Status Flag
The EOCF bit is set when:
This flag is cleared by a read of the MSC register followed by an access of CMD2 or CMD4 or by the
DMA transfer.
0
1
CMT Clock Divide Prescaler
The Secondary Prescaler causes the CMT to be clocked at the IF signal frequency, or the IF frequency
divided by 2 ,4, or 8. Since these bits are not double buffered, they should not be changed during a
transmission.
00
01
10
11
Extended Space Enable
The EXSPC bit enables extended space operation.
0
1
7
0
• The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
• At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match
No end of modulation cycle occurrence since flag last cleared
End of modulator cycle has occurred
Extended space disabled
Extended space enabled
IF ÷ 1
IF ÷ 2
IF ÷ 4
IF ÷ 8
transmission.
occurs between the contents of the space period register and the down counter. At this time, the
counter is initialized with the (possibly new) contents of the mark period buffer, CMT_CMD1 and
CMT_CMD2, and the space period register is loaded with the (possibly new) contents of the space
period buffer, CMT_CMD3 and CMT_CMD4.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
CMTDIV
CMT_MSC field descriptions
Table continues on the next page...
0
5
EXSPC
0
4
Description
BASE
0
3
FSK
0
2
Freescale Semiconductor, Inc.
EOCIE
0
1
MCGEN
0
0