MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 827

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.3.19 Input Capture Filter Control (FTMx_FILTER)
This register selects the filter value for the inputs of channels.
Channels 4, 5, 6 and 7 do not have an input filter.
Freescale Semiconductor, Inc.
FAULTF1
FAULTF0
Field
1
0
Writing to the FILTER register has immediate effect and must
be done only when the channels 0, 1, 2, and 3 are not in input
modes. Failure to do this could result in a missing valid signal.
0
1
Fault Detection Flag 1
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF1 by reading the FMS register while FAULTF1 is set and then writing a 0 to FAULTF1 while
there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF1 has no
effect. FAULTF1 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF1 remains set after the clearing sequence is completed for
the earlier fault condition.
0
1
Fault Detection Flag 0
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF0 by reading the FMS register while FAULTF0 is set and then writing a 0 to FAULTF0 while
there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF0 has no
effect. FAULTF0 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF0 remains set after the clearing sequence is completed for
the earlier fault condition.
0
1
No fault condition was detected at the fault input.
A fault condition was detected at the fault input.
No fault condition was detected at the fault input.
A fault condition was detected at the fault input.
No fault condition was detected at the fault input.
A fault condition was detected at the fault input.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
FTMx_FMS field descriptions (continued)
NOTE
Description
Chapter 36 FlexTimer (FTM)
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