MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 958

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
The possible duty cycle options depend upon the number of counts required to complete
the carrier period. For example, 1.6 MHz signal has a period of 625 ns and will therefore
require 5 x 125 ns counts to generate. These counts may be split between high and low
times, so the duty cycles available will be 20% (one high, four low), 40% (two high, three
low), 60% (three high, two low) and 80% (four high, one low).
For lower frequency signals with larger periods, higher resolution (as a percentage of the
total period) duty cycles are possible.
The carrier signal is generated by counting a register-selected number of input clocks
(125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The
period is determined by the total number of clocks counted. The duty cycle is determined
by the ratio of high time clocks to total clocks counted. The high and low time values are
user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the
generation of dual frequency FSK (frequency shift keying) protocols without CPU
intervention.
MSC[MCGEN] bit must be set and MSC[BASE] bit must be cleared to enable carrier
generator clocks. When MSC[BASE] bit is set, the carrier output to the modulator is held
high continuously. Following figure represents the block diagram of the clock generator.
958
Clock
(MHz)
Bus
8
8
8
8
Only non-zero data values are allowed. The carrier generator
will not work if any of the count values are equal to zero.
MSC[CMTDIV]
00
01
10
11
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 39-17. Clock Divider
Carrier Generator
Resolution (μs)
Note
0.125
0.25
0.5
1.0
Generator Period
Min. Carrier
0.25
(μs)
0.5
1.0
2.0
Freescale Semiconductor, Inc.
Modulator Period
Min.
(μs)
1.0
2.0
4.0
8.0