MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 995

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
SOFTRST
WAKMSK
NOTRDY
FRZACK
HALT
Field
28
27
26
25
24
are used as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the minimum number
of peripheral clocks per CAN bit as described in the table "Minimum Ratio Between Peripheral Clock
Frequency and CAN Bit Rate" (in section "Arbitration and Matching Timing"). This bit can only be written
in Freeze mode as it is blocked by hardware in other modes.
0
1
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after initializing
the Message Buffers and Control Register. No reception or transmission is performed by FlexCAN before
this bit is cleared. Freeze Mode cannot be entered while FlexCAN is in a low power mode.
0
1
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable Mode, Doze Mode, Stop Mode or Freeze
Mode. It is negated once FlexCAN has exited these modes.
0
1
Wake Up Interrupt Mask
This bit enables the Wake Up Interrupt generation.
0
1
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped
registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR1, ESR2,
IMASK1, IMASK2, IFLAG1, IFLAG2 and CRCR. Configuration registers that control the interface to the
CAN bus are not affected by soft reset. The following registers are unaffected: CTRL1, CTRL2, RXIMR0–
RXIMR63, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all Message Buffers.
The SOFTRST bit can be asserted directly by the CPU when it writes to the MCR Register, but it is also
asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has to
follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate
its effect. The SOFTRST bit remains asserted while reset is pending, and is automatically negated when
reset completes. Therefore, software can poll this bit to know when the soft reset has completed.
Soft reset cannot be applied while clocks are shut down in a low power mode. The module should be first
removed from low power mode, and then soft reset can be applied.
0
1
Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze
Mode request cannot be granted until current transmission or reception processes have finished.
Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered Freeze
Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN prescaler is running
Rx FIFO not enabled
Rx FIFO enabled
No Freeze Mode request.
Enters Freeze Mode if the FRZ bit is asserted.
FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode.
FlexCAN module is either in Disable Mode, Doze Mode, Stop Mode or Freeze Mode.
Wake Up Interrupt is disabled.
Wake Up Interrupt is enabled.
No reset request
Resets the registers affected by soft reset.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CANx_MCR field descriptions (continued)
Table continues on the next page...
Description
Chapter 41 CAN (FlexCAN)
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