MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1006

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory Map/Register Definition
FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error
Active’ or ‘Error Passive’ flag, delay its transmission start time (‘Error Passive’) and
avoid any influence on the bus when in ‘Bus Off’ state. The following are the basic rules
for FlexCAN bus state transitions.
Addresses: CAN0_ECR is 4002_4000h base + 1Ch offset = 4002_401Ch
1006
Bit
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R
• If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
• If the FlexCAN state is ‘Error Passive’, and either TXERRCNT or RXERRCNT
• If the value of TXERRCNT increases to be greater than 255, the FLTCONF field in
• If FlexCAN is in ‘Bus Off’ state, then TXERRCNT is cascaded together with another
• If during system start-up, only one node is operating, then its TXERRCNT increases
• If the RXERRCNT increases to a value greater than 127, it is not incremented
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128, the FLTCONF field in the Error and Status Register is updated to reflect ‘Error
Passive’ state.
decrements to a value less than or equal to 127 while the other already satisfies this
condition, the FLTCONF field in the Error and Status Register is updated to reflect
‘Error Active’ state.
the Error and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt
may be issued. The value of TXERRCNT is then reset to zero.
internal counter to count the 128th occurrences of 11 consecutive recessive bits on
the bus. Hence, TXERRCNT is reset to zero and counts in a manner where the
internal counter counts 11 such bits and then wraps around while incrementing the
TXERRCNT. When TXERRCNT reaches the value of 128, the FLTCONF field in
the Error and Status Register is updated to be ‘Error Active’ and both error counters
are reset to zero. At any instance of dominant bit following a stream of less than 11
consecutive recessive bits, the internal counter resets itself to zero without affecting
the TXERRCNT value.
in each message it is trying to transmit, as a result of acknowledge errors (indicated
by the ACKERR bit in the Error and Status Register). After the transition to ‘Error
Passive’ state, the TXERRCNT does not increment anymore by acknowledge errors.
Therefore the device never goes to the ‘Bus Off’ state.
further, even if more errors are detected while being a receiver. At the next
successful message reception, the counter is set to a value between 119 and 127 to
resume to ‘Error Active’ state.
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K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
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RXERRCNT
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Freescale Semiconductor, Inc.
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TXERRCNT
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