MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1218

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
44.4.2.10.3 Match address operation
Match address operation is enabled when the C4[MAEN1] or C4[MAEN2] bit is set. In
this function, a frame received by the RX pin with a logic 1 in the bit position
immediately preceding the stop bit is considered an address and is compared with the
associated MA1 or MA2 register. The frame is only transferred to the receive buffer, and
S1[RDRF] is set, if the comparison matches. All subsequent frames received with a logic
0 in the bit position immediately preceding the stop bit are considered to be data
associated with the address and are transferred to the receive data buffer. If no marked
address match occurs then no transfer is made to the receive data buffer, and all following
frames with logic zero in the bit position immediately preceding the stop bit are also
discarded. If both the C4[MAEN1] and C4[MAEN2] bits are negated, the receiver
operates normally and all data received is transferred to the receive data buffer.
Match Address operation functions in the same way for both MA1 and MA2 registers.
Address match operation is not supported when C7816[ISO_7816E] is set/enabled.
44.4.3 Baud rate generation
A 13-bit modulus counter and a 5-bit fractional fine-adjust counter in the baud rate
generator derive the baud rate for both the receiver and the transmitter. The value from 1
to 8191 written to the SBR[12:0] bits determines the module clock divisor. The SBR bits
are in the UART baud rate registers (BDH and BDL). The baud rate clock is
synchronized with the module clock and drives the receiver. The fractional fine-adjust
counter adds fractional delays to the baud rate clock to allow fine trimming of the baud
rate to match the system baud rate. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to two sources of error:
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• If only one of C4[MAEN1] and C4[MAEN2] is asserted, a marked address is
• If C4[MAEN1] and C4[MAEN2] are asserted, a marked address is compared with
• Integer division of the module clock may not give the exact target frequency. This
• Synchronization with the module clock can cause phase shift.
compared only with the associated match register and data is transferred to the
receive data buffer only on a match.
both match registers and data is transferred only on a match with either register.
error can be reduced by means of the fine-adjust counter.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.