MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 668

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Register Definition
668
ADLSMP
ADICLK
MODE
ADIV
Field
6–5
3–2
1–0
4
0
1
Clock divide select
ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
00
01
10
11
Sample time configuration
ADLSMP selects between different sample times based on the conversion mode selected. This bit adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power
consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample
time.
0
1
Conversion mode selection
MODE bits are used to select the ADC resolution mode.
00
01
10
11
Input clock select
ADICLK bits select the input clock source to generate the internal clock, ADCK. Note that when the
ADACK clock source is selected, it is not required to be active prior to conversion start. When it is
selected and it is not active prior to a conversion start (ADACKEN=0), the asynchronous clock is activated
at the start of a conversion and shuts off when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00
01
10
11
Normal power configuration.
Low power configuration. The power is reduced at the expense of maximum clock speed.
Short sample time.
Long sample time.
The divide ratio is 1 and the clock rate is input clock.
The divide ratio is 2 and the clock rate is (input clock)/2.
The divide ratio is 4 and the clock rate is (input clock)/4.
The divide ratio is 8 and the clock rate is (input clock)/8.
When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion
with 2's complement output.
When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion
with 2's complement output.
When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion
with 2's complement output.
When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion
with 2's complement output.
Bus clock.
Bus clock divided by 2.
Alternate clock (ALTCLK).
Asynchronous clock (ADACK).
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
ADCx_CFG1 field descriptions (continued)
Description
Freescale Semiconductor, Inc.