MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 894

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
36.4.18 Initialization
The initialization forces the CHnOI bit value to the channel (n) output when a one is
written to the INIT bit.
The initialization depends on COMP and DTEN bits. The following table shows the
values that channels (n) and (n+1) are forced by initialization when the COMP and
DTEN bits are zero.
The following table shows the values that channels (n) and (n+1) are forced by
initialization when (COMP = 1) or (DTEN = 1).
36.4.19 Features Priority
The following figure shows the priority of the features used at the generation of channels
(n) and (n+1) outputs signals.
894
CH(n)OI
CH(n)OI
Table 36-245. Initialization Behavior when (COMP = 0 and DTEN = 0)
Table 36-246. Initialization Behavior when (COMP = 1 or DTEN = 1)
0
0
1
1
0
1
It is expected that the polarity control be used only in combine
mode.
It is expected that the initialization feature be used only in
combine mode and with disabled FTM counter (see the
description of the
register).
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CH(n+1)OI
CH(n+1)OI
CLKS
0
1
0
1
X
X
field in the Status and Control
Note
Note
is forced to zero
is forced to zero
is forced to one
is forced to one
is forced to zero
is forced to one
Channel (n) Output
Channel (n) Output
is forced to zero
is forced to one
is forced to zero
is forced to one
is forced to one
is forced to zero
Channel (n+1) Output
Channel (n+1) Output
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