MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 895

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

36.4.20 Channel Trigger Output
If CHjTRIG = 1 (where j = 0, 1, 2, 3, 4, or 5), then the FTM generates a trigger when the
channel (j) match occurs (FTM counter = C(j)V).
The channel trigger output provides a trigger signal that is used for on-chip modules.
Freescale Semiconductor, Inc.
Figure 36-237. Priority of the Features Used at the Generation of Channels (n) and (n+1)
NOTE
The channels (n) and (n+1) are in output compare, EPWM, CPWM or combine modes.
COMBINE(m)
FTM counter
DECAPEN
QUADEN
CPWMS
channel (n+1)
generation of
output signal
generation of
output signal
channel (n)
ELS(n+1)B
ELS(n+1)A
MS(n+1)B
MS(n+1)A
C(n+1)V
ELS(n)B
ELS(n)A
MS(n)B
MS(n)A
C(n)V
It is expected that the initialization feature (Initialization) is not
used with inverting (Inverting) and software output control
(Software Output
CH(n+1)OI
initialization
CH(n)OI
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
complementary
COMP(m)
mode
Control) features.
pair channels (m) - channels (n) and (n+1)
Outputs Signals
INV(m)EN
inverting
Note
CH(n+1)OCV
CH(n+1)OC
CH(n)OCV
CH(n)OC
software
control
output
deadtime
DTEN(m)
insertion
CH(n+1)OM FAULTEN(m)
CH(n)OM
output
mask
Chapter 36 FlexTimer (FTM)
control
fault
POL(n+1)
polarity
control
POL(n)
channel
channel
output
output
signal
signal
(n+1)
(n)
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