MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 900

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
36.4.24 Dual Edge Capture Mode
The dual edge capture mode is selected if FTMEN = 1 and DECAPEN = 1. This mode
allows to measure a pulse width or period of the signal on the input of channel (n) of a
channel pair. The channel (n) filter can be active in this mode when n is 0 or 2.
The MS(n)A bit defines if the dual edge capture mode is one-shot or continuous.
The ELS(n)B:ELS(n)A bits select the edge that is captured by channel (n), and ELS(n
+1)B:ELS(n+1)A bits select the edge that is captured by channel (n+1). If both
ELS(n)B:ELS(n)A and ELS(n+1)B:ELS(n+1)A bits select the same edge, then it is the
period measurement. If these bits select different edges, then it is a pulse width
measurement.
In the dual edge capture mode, only channel (n) input is used and channel (n+1) input is
ignored.
If the selected edge by channel (n) bits is detected at channel (n) input, then CH(n)F bit is
set and the channel (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by
channel (n+1) bits is detected at channel (n) input and (CH(n)F = 1), then CH(n+1)F bit is
set and the channel (n+1) interrupt is generated (if CH(n+1)IE = 1).
900
CHnIE
channel (n) input
system clock
0
1
* Filtering function for dual edge capture mode is only available in the channels 0 and 2
CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and
then writing a 0 to CHnF bit.
CHnF bit is cleared when the channel DMA transfer is done.
How CHnF Bit Can Be Cleared
Figure 36-244. Dual Edge Capture Mode Block Diagram
D
CLK
synchronizer
Q
Table 36-248. Clear CHnF Bit when DMA = 1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
D
CLK
Q
Filter*
enabled?
is filter
0
1
ELS(n+1)B:ELS(n+1)A
Dual edge capture
ELS(n)B:ELS(n)A
DECAPEN
mode logic
FTMEN
DECAP
MS(n)A
FTM counter
CH(n+1)IE
CH(n+1)F
C(n+1)V[15:0]
CH(n)IE
CH(n)F
C(n)V[15:0]
Freescale Semiconductor, Inc.
channel (n+1)
channel (n)
interrupt
interrupt