MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 236

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Memory map and register definition
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)
Addresses: PORTA_GPCLR is 4004_9000h base + 80h offset = 4004_9080h
236
Bit
W
R
31
0
GPWD
GPWE
31–16
15–0
Field
SRE
Field
PE
PS
30
2
1
0
0
PORTB_GPCLR is 4004_A000h base + 80h offset = 4004_A080h
PORTC_GPCLR is 4004_B000h base + 80h offset = 4004_B080h
PORTD_GPCLR is 4004_C000h base + 80h offset = 4004_C080h
PORTE_GPCLR is 4004_D000h base + 80h offset = 4004_D080h
29
0
28
0
Slew Rate Enable
Slew Rate configuration is valid in all digital pin muxing modes.
0
1
Pull Enable
Pull configuration is valid in all digital pin muxing modes.
0
1
Pull Select
Pull configuration is valid in all digital pin muxing modes.
0
1
Global Pin Write Enable
When set, causes bits [15:0] of the corresponding Pin Control Register (15 through 0) to update with the
value in the Global Pin Write Data field.
Global Pin Write Data
Value to be written to bits [15:0] of all Pin Control Registers that are enabled by the Global Pin Write
Enable field, provided the corresponding register has not been locked.
27
0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured
as a digital input.
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable
Register bit is set.
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable
Register bit is set.
26
0
25
0
GPWE
24
PORTx_PCRn field descriptions (continued)
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
23
0
22
PORTx_GPCLR field descriptions
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
GPWD
0
8
0
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
3
0
2
0
1
0
0