MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1308

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
The CRC polynomials for the CMD are as follows:
Generator polynomial: G(x) = x
M(x) = (first bit) * x
CRC[6:0] = Remainder [(M(x) * x
45.5.3.4 Data agent
The data agent deals with the transactions on the eight data lines. Moreover, this module
also detects the busy state on the DAT[0] line, and generate the read wait state by the
request from the transceiver. The CRC polynomials for the DAT are as follows:
Generator polynomial: G(x) = x
M(x) = (first bit) * x
CRC[15:0] = Remainder [(M(x) * x
45.5.4 Clock & reset manager
This module controls all the reset signals within the SDHC.
There are four kinds of reset signals within SDHC:
All these signals are fed into this module and stable signals are generated inside the
module to reset all other modules. The module also gates off all the inside signals.
There are three clocks inside the SDHC:
1308
CRC_IN
+1
1. Hardware reset.
2. Software reset for all.
3. Software reset for the data part.
4. Software reset for the command part.
ZERO
ZERO
CLR_CRC
Bus [0]
CRC
n
n
+ (second bit) * x
+ (second bit) * x
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Figure 45-34. Command CRC Shift Register
Bus [1]
CRC
7
16
7
+ x
) / G(x)]
16
+ x
) / G(x)]
3
12
Bus [2]
+ 1
CRC
+ x
5
n-1
n-1
+...+ (last bit) * x
+...+ (last bit) * x
Bus [3]
CRC OUT
CRC OUT
CRC
Bus [4]
CRC
0
0
Freescale Semiconductor, Inc.
Bus [5]
CRC
Bus [6]
CRC