MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1502

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
49.4.4.1 LCD power supply configuration
The LCD bias voltages can be internally derived from V
voltage source (should never be externally driven to any level other than V
to V
supply 1.0 or 1.67 V (V
the power state of the LCD controller that depends on the configuration of the
VSUPPLY[1:0], CPSEL and RVEN bits. The table shows all possible configurations of
the LCD power supply. All other combinations of the configuration bits above are not
permissible LCD power supply modes and should be avoided.
1502
V
internally for 3 V or 5 V
glass operation.
LCD operational state
LL2
VSUPPLY[1:0]
connected to V
LL3
11
, internally derived from a regulated voltage source that can be configured to
Table 49-37. LCD power supply configuration options (continued)
The charge pump is optimized for 1/3 bias mode operation
only.
The charge pump requires external capacitance for its
operation. To provide this external capacitance, the V
V
ceramic capacitor be used. Proper orientation is imperative
when using a polarized capacitor. The recommended value for
the external capacitor is 0.1 μF.
cap2
DD
external pins are provided. It is recommended that a
For 3 V glass operation, V
equal to 2 V.
For 5 V glass operation, V
equal to 3.33 V.
Charge pump is used to generate V
and V
LCD power supply configuration
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
IREG
LL3
Table 49-38. LCD power supply options
Drive V
Drive V
.
). The following table provides a more detailed description of
LL1
LL3
Configuration
Table continues on the next page...
internally from V
externally from V
or
DD
DD
must be
must be
Note
IREG
DD
LL1
00
DD
0
powersw1
, internally derived from a
X
cap1
Freescale Semiconductor, Inc.
and
0
powersw2
1
DD
) connected
0