MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 688

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
31.4.3 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the
reference voltage (V
positive reference that must be between the minimum Ref Voltage High and V
ground reference that must be at the same potential as V
(V
selected using the REFSEL bits in the SC2 register. The alternate (V
voltage reference pair may select additional external pins or internal sources depending
on MCU configuration. Refer to the Chip Configuration information on the Voltage
References specific to this MCU.
31.4.4 Hardware trigger and channel selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT,
that is enabled when the ADTRG bit is set and a hardware trigger select event
(ADHWTSn) has occurred. This source is not available on all MCUs. Refer to the Chip
Configuration chapter for information on the ADHWT source and the ADHWTSn
configurations specific to this MCU.
When a ADHWT source is available and hardware trigger is enabled (ADTRG=1), a
conversion is initiated on the rising edge of ADHWT after a hardware trigger select event
(ADHWTSn) has occurred. If a conversion is in progress when a rising edge of a trigger
occurs, the rising edge is ignored. In continuous convert configuration, only the initial
rising edge to launch continuous conversions is observed, and until conversion gets
aborted the ADC continues to do conversions on the same ADC status and control
register that initiated the conversion. The hardware trigger function operates in
conjunction with any of the conversion modes and configurations.
The hardware trigger select event (ADHWTSn) must be set prior to the receipt of the
ADHWT signal. If these conditions are not met, the converter may ignore the trigger or
use the incorrect configuration. If a hardware trigger select event gets asserted during a
conversion, it must stay asserted until the end of current conversion and remain set until
the receipt of the ADHWT signal to trigger a new conversion. The channel and status
fields selected for the conversion depend on the active trigger select signal (ADHWTSA
active selects SC1A; ADHWTSn active selects SC1n).
688
REFH
and V
Asserting more than one hardware trigger select signal
(ADHWTSn) at the same time results in unknown results. To
avoid this, select only one hardware trigger select signal
(ADHWTSn) prior to the next intended conversion.
REFL
) and alternate (V
REFSH
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
and V
REFSL
ALTH
) used for conversions. Each pair contains a
and V
Note
ALTL
). These voltage references are
SSA
. The two pairs are external
Freescale Semiconductor, Inc.
ALTH
and V
DDA
ALTL
, and a
)