MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 418

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Reset
Memory map/register definition
21.3.1 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through without regard to priority.
Address: DMA_CR is 4000_8000h base + 0h offset = 4000_8000h
418
Bit
W
R
4000_91FC
4000_91FE
4000_91FE
4000_91F6
4000_91F8
Absolute
address
Reserved
(hex)
31
0
31–18
Field
CX
17
30
0
29
0
DMA_TCD15_CITER_ELINKNO
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD15_DLASTSGA)
TCD Control and Status (DMA_TCD15_CSR)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD15_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD15_BITER_ELINKNO)
28
0
For proper operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
This read-only field is reserved and always has the value zero.
Cancel Transfer
27
0
26
0
25
0
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
Register name
22
0
DMA memory map (continued)
21
0
DMA_CR field descriptions
Table continues on the next page...
20
0
19
0
18
0
NOTE
17
0
16
0
15
0
Description
14
0
13
0
12
0
(in bits)
Width
0
16
32
16
16
16
11
0
10
0
Access
0
9
R/W
R/W
R/W
R/W
R/W
0
8
Freescale Semiconductor, Inc.
0
7
Reset value
Undefined
Undefined
Undefined
Undefined
Undefined
0
6
0
5
4
0
0
0
3
Section/
21.3.27/
21.3.28/
21.3.29/
21.3.30/
21.3.31/
0
2
page
448
449
450
452
453
0
1
0
0
0

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