MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1498

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
49.4.2 WFyTOx registers
For a segment on the LCD panel to be displayed, data must be written to the WFyTOx
registers. For LCD pins enabled as frontplanes, each bit in the WFyTOx registers
corresponds to a segment on an LCD panel. The different phases (A-H) represent the
different backplanes of the LCD panel. The selected LCD duty cycle controls the number
of implemented phases. Refer to the
follow the sequence shown.
For LCD pins enabled as a backplane, the WFyTOx register assigns the phase in which
the backplane pin is active. This is how backplane assignment is done.
An example of normal operation follows.
To enable LCD_P0 to operate as backplane 0.
This configures LCD_P0 to operate as a backplane that is active in phase A.
For LCD pins enabled as a frontplane:
49.4.3 LCD display modes
The LCD controller can be configured to implement several different display modes. In
the LCD auxiliary register (AR), the bits ALT and BLANK configure the different
display modes:
Normal display mode (default)
Blank display mode
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1. Enable the LCD_P0 by setting PEN0 bit in the PENL register, PENL = 0x00000001.
2. Configure LCD_P0 as a backplane pin by setting the BPEN0 bit in the BPEN0
3. The WF0 bit in the WF3TO0 register is set to associate LCD_P0 with backplane
• Writing 1 to a given WF location results in the corresponding display segment being
• Writing 0 to a given location results in the corresponding display segment being
The LCD segments are controlled by the data placed in the WFyTOx registers, as
described in the preceding section.
The WF data is bypassed and the frontplane and backplane pins are configured to clear
all segments.
register.
phase A, WF3to0 =0x00000001.
driven with the differential root mean square (RMS) voltage necessary to turn the
segment on during the phase selected.
driven with the differential RMS voltage necessary to turn the segment off during the
phase selected.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 49-30
for normal LCD operation the phases
Freescale Semiconductor, Inc.