MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 403

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

In the discussion of this module, n is used to reference the channel number.
21.2 Modes of operation
The eDMA operates in the following modes:
21.3 Memory map/register definition
The eDMA's programming model is partitioned into two regions:
Freescale Semiconductor, Inc.
Normal
Debug
Wait
• Channel completion reported via optional interrupt requests
• Optional support for scatter/gather DMA processing
• Support for complex data structures
• Support to cancel transfers via software
• One interrupt per channel, optionally asserted at completion of major iteration
• Optional error terminations per channel and logically summed together to form
count
one error interrupt to the interrupt controller
Mode
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 21-3. Modes of operation
In Normal mode, the eDMA transfers data between a source
and a destination. The source and destination can be a
memory block or an I/O block capable of operation with the
eDMA.
A service request initiates a transfer of a specific number of
bytes (NBYTES) as specified in the transfer control descriptor
(TCD). The minor loop is the sequence of read-write
operations that transfers these NBYTES per service request.
Each service request executes one iteration of the major
loop, which transfers NBYTES of data.
DMA operation is configurable in Debug mode via the control
register:
Before entering Wait mode, the DMA attempts to complete its
current transfer. After the transfer completes, the device
enters Wait mode.
• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data.
Chapter 21 Direct Memory Access Controller (eDMA)
If Debug mode is entered while a channel is active, the
eDMA continues operation until the channel retires.
Description
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