MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 58

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Module Functional Categories
2.3.7 Timer modules
The following timer modules are available on this device:
58
12-bit digital-to-analog converters (DAC)
Voltage reference (VREF)
Programmable delay block (PDB)
Flexible timer modules (FTM)
Module
Module
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 2-7. Analog modules (continued)
Low-power general-purpose DAC, whose output can be placed on an external pin
or set as one of the inputs to the analog comparator or ADC.
Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF
can be used in medical applications, such as glucose meters, to provide a
reference voltage to biosensors or as a reference to analog peripherals, such as
the ADC, DAC, or CMP.
Table 2-8. Timer modules
Table continues on the next page...
• 16-bit resolution
• 3-bit prescaler
• Positive transition of trigger event signal initiates the counter
• Supports two triggered delay output signals, each with an independently-
• Outputs can be OR'd together to schedule two conversions from one input
• Continuous-pulse output or single-shot mode supported, each output is
• Supports bypass mode
• Supports DMA
• Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up
• Input capture, output compare, and edge-aligned and center-aligned PWM
• Operation of FTM channels as pairs with equal outputs, pairs with
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed
• Quadrature decoder with input filters, relative position counting, and interrupt
• DMA support for FTM events
controlled delay from the trigger event
trigger event and can schedule precise edge placement for a pulsed output.
This feature is used to generate the control signal for the CMP windowing
feature and output to a package pin if needed for applications, such as
critical conductive mode power factor correction.
independently enabled, with possible trigger events
or up-down
modes
complimentary outputs, or independent channels with independent outputs
counter, or detected fault condition
on position count or capture of position count on external event
Description
Description
Freescale Semiconductor, Inc.