MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 991

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The complete memory map for a FlexCAN module is shown in the following table.
The address space occupied by FlexCAN has 128 bytes for registers starting at the
module base address, followed by embedded RAM starting at address 0x0080.
Each individual register is identified by its complete name and the corresponding
mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the
registers can be configured to have either Supervisor or Unrestricted access by
programming the SUPV bit in the MCR Register. These registers are identified as S/U in
the Access column of
The registers IFLAG2 and IMASK2 are considered reserved space depending on the
number of Mailboxes available in the device.
Freescale Semiconductor, Inc.
Individual Matching Elements Update Register (IMUER)
Rx Mailboxes Global Mask Register (RXMGMASK)
Rx FIFO Global Mask Register (RXFGMASK)
Rx Buffer 14 Mask Register (RX14MASK)
Rx Buffer 15 Mask Register (RX15MASK)
Free Running Timer Register (TIMER)
Rx FIFO Information Register (RXFIR)
Module Configuration Register (MCR)
Interrupt Masks 2 Register (IMASK2)
Interrupt Masks 1 Register (IMASK1)
Error and Status 1 Register (ESR1)
Interrupt Flags 2 Register (IFLAG2)
Interrupt Flags 1 Register (IFLAG1)
Error and Status 2 Register (ESR2)
Lost Rx Frames Register (LRFR)
Error Counter Register (ECR)
Rx Individual Mask Registers
Control 1 Register (CTRL1)
Control 2 Register (CTRL2)
CRC Register (CRCR)
Message Buffers
Table
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register
Table 41-2. Module Memory Map
41-2.
Access Type
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
Affected by
Hard Reset
Chapter 41 CAN (FlexCAN)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Affected by
Soft Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
991