MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1010

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
1010
FLTCONF
BOFFINT
RXWRN
IDLE
Field
5–4
RX
TX
8
7
6
3
2
This bit indicates when repetitive errors are occurring during message transmission. This bit is not
updated during Freeze mode.
0
1
Rx Error Warning
This bit indicates when repetitive errors are occurring during message reception. This bit is not updated
during Freeze mode.
0
1
This bit indicates when CAN bus is in IDLE state. See the table in the overall CAN_ESR1 register
description.
0
1
FlexCAN in Transmission
This bit indicates if FlexCAN is transmitting a message. See the table in the overall CAN_ESR1 register
description.
0
1
Fault Confinement State
This 2-bit field indicates the Confinement State of the FlexCAN module.
If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the
FLTCONF field will indicate “Error Passive”. The very same delay affects the way how FLTCONF reflects
an update to ECR register by the CPU. It may be necessary up to one CAN bit time to get them coherent
again.
Since the Control Register is not affected by soft reset, the FLTCONF field will not be affected by soft
reset if the LOM bit is asserted.
00
01
1x
FlexCAN in Reception
This bit indicates if FlexCAN is receiving a message. See the table in the overall CAN_ESR1 register
description.
0
1
‘Bus Off’ Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control Register
(BOFFMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’
has no effect.
No such occurrence
TXERRCNT is greater than or equal to 96.
No such occurrence
RXERRCNT is greater than or equal to 96.
No such occurrence
CAN bus is now IDLE.
FlexCAN is not transmitting a message.
FlexCAN is transmitting a message.
FlexCAN is not receiving a message.
FlexCAN is receiving a message.
Error Active
Error Passive
Bus Off
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
CANx_ESR1 field descriptions (continued)
Table continues on the next page...
Description
Freescale Semiconductor, Inc.