MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 951

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

39.6.5 CMT Output Control Register (CMT_OC)
This register is used to control the IRO signal of the CMT module.
Address: CMT_OC is 4006_2000h base + 4h offset = 4006_2004h
Freescale Semiconductor, Inc.
Reserved
CMTPOL
IROPEN
IROL
Reset
Field
Read
4–0
Write
7
6
5
Bit
IROL
IRO Latch Control
Reading IROL reads the state of the IRO latch. Writing to IROL changes the state of the CMT_IRO signal
when MSC[MCGEN] bit is cleared and the IROPEN bit is set.
CMT Output Polarity
The CMTPOL bit controls the polarity of the CMT_IRO signal of the CMT.
0
1
IRO Pin Enable
The IROPEN bit is used to enable and disable the CMT_IRO signal. When CMT_IRO signal is enabled, it
is an output that drives out either the CMT transmitter output or the state of the IROL bit depending on
whether MSC[MCGEN] bit is set or not. Also, the state of the output is either inverted or not depending on
the state of the CMTPOL bit. When CMT_IRO signal is disabled, it is in a high impedance state so as not
to draw any current. This signal is disabled during reset.
0
1
This read-only field is reserved and always has the value zero.
7
0
CMT_IRO signal is active low
CMT_IRO signal is active high
CMT_IRO signal disabled
CMT_IRO signal enabled as output
CMTPOL
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
6
CMT_OC field descriptions
IROPEN
0
5
0
4
Description
Chapter 39 Carrier Modulator Transmitter (CMT)
0
3
0
0
2
0
1
0
0
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