MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 851

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Firstly the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block (see the following figure). When there is a state
change in the input signal, the 5-bit counter is reset and starts counting up. As long as the
new state is stable on the input, the counter continues to increment. If the 5-bit counter
overflows (the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of
the input signal is validated. It is then transmitted as a pulse edge to the edge detector.
If the opposite edge appears on the input signal before validation (counter overflow), the
counter is reset. At the next input transition, the counter starts counting again. Any pulse
that is shorter than the minimum value selected by CHnFVAL[3:0] bits (× 4 system
clocks) is regarded as a glitch and is not passed on to the edge detector. A timing diagram
of the input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then the
input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system clocks)
plus a further 4 rising edges of the system clock (two rising edges to the synchronizer,
one rising edge to the filter output plus one more to the edge detector). In other words,
CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on
the channel input.
The clock for the 5-bit counter in the channel input filter is the system clock divided by 4.
Freescale Semiconductor, Inc.
channel (n) input after
the synchronizer
system clock divided by 4
system clock
after the synchronizer
CHnFVAL[3:0] = 0010
channel (n) input
(binary value)
5-bit counter
filter output
the filter counter
Logic to control
Figure 36-177. Channel Input Filter Example
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
divided by 4
Figure 36-176. Channel Input Filter
5-bit up counter
Logic to define
the filter output
CHnFVAL[3:0]
Chapter 36 FlexTimer (FTM)
S
C
CLK
Q
Time
filter output
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