MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 769

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

35.3.1 Status and Control Register (PDBx_SC)
Addresses: PDB0_SC is 4003_6000h base + 0h offset = 4003_6000h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
Reserved
SWTRIG
R
R
PDBEIE
LDMOD
31–20
19–18
Field
17
16
31
15
0
0
30
14
0
0
PRESCALER
This read-only field is reserved and always has the value zero.
Load Mode Select
Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to
LDOK.
00
01
10
11
PDB Sequence Error Interrupt Enable
This bit enables the PDB sequence error interrupt. When this bit is set, any of the PDB channel sequence
error flags generates a PDB sequence error interrupt.
0
1
Software Trigger
When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit
reset and restarts the counter. Writing 0 to this bit has no effect. Reading this bit results 0.
PDB sequence error interrupt disabled.
PDB sequence error interrupt enabled.
29
13
The internal registers are loaded with the values from their buffers immediately after 1 is written to
LDOK.
The internal registers are loaded with the values from their buffers when the PDB counter reaches
the MOD register value after 1 is written to LDOK.
The internal registers are loaded with the values from their buffers when a trigger input event is
detected after 1 is written to LDOK.
The internal registers are loaded with the values from their buffers when either the PDB counter
reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
28
12
0
0
27
11
0
0
PDBx_SC field descriptions
Table continues on the next page...
26
10
TRGSEL
0
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
Chapter 35 Programmable Delay Block (PDB)
21
0
0
5
20
0
0
0
4
19
0
0
3
LDMOD
MULT
18
0
0
2
17
0
0
1
16
0
0
0
0
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