MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 105

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

1. Interleaved with ADC1_DP3 and ADC1_DM3
2. Interleaved with ADC1_DP3
3. Interleaved with ADC1_DP0 and ADC1_DM0
4. Interleaved with ADC1_DP0
5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
6. Interleaved with ADC1_SE8
7. Interleaved with ADC1_SE9
8. Interleaved with ADC1_DM3
9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this
3.7.1.4 ADC1 Connections/Channel Assignment
3.7.1.4.1 ADC1 Channel Assignment for 80/81-Pin Packages
Freescale Semiconductor, Inc.
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
00100
00101
00110
for details.
ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data
sheet for the bandgap voltage (V
5
5
5
5
5
5
5
(SC1n[ADCH])
(SC1n[ADCH])
ADC Channel
ADC Channel
As indicated in the following tables, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DAD0
DAD1
DAD2
DAD3
AD4a
AD5a
AD6a
AD7a
AD4b
AD5b
AD6b
Channel
Channel
BG
) specification.
Table continues on the next page...
NOTE
Reserved
Temperature Sensor (Diff)
Bandgap (Diff)
Reserved
-VREFH (Diff)
Reserved
Module Disabled
ADC1_DP0 and ADC1_DM0
Reserved
PGA1_DP and PGA1_DM
ADC1_DP3 and ADC1_DM3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(SC1n[DIFF]= 1)
(SC1n[DIFF]= 1)
Input signal
Input signal
9
1
3
Chapter 3 Chip Configuration
Reserved
Temperature Sensor (S.E)
Bandgap (S.E)
Reserved
VREFH (S.E)
VREFL
Module Disabled
ADC1_DP0
Reserved
PGA1_DP
ADC1_DP3
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ADC1_SE4b
ADC1_SE5b
ADC1_SE6b
(SC1n[DIFF]= 0)
(SC1n[DIFF]= 0)
Input signal
Input signal
2
4
9
105