MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 775

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Reset
35.3.7 Channel n Delay 0 Register (PDBx_CHDLY0)
Addresses: PDB0_CH0DLY0 is 4003_6000h base + 18h offset = 4003_6018h
35.3.8 Channel n Delay 1 Register (PDBx_CHDLY1)
Addresses: PDB0_CH0DLY1 is 4003_6000h base + 1Ch offset = 4003_601Ch
Freescale Semiconductor, Inc.
Bit
Bit
W
W
R
R
Reserved
Reserved
31
31
0
0
31–16
31–16
15–0
15–0
Field
Field
DLY
DLY
30
30
0
0
PDB0_CH1DLY0 is 4003_6000h base + 40h offset = 4003_6040h
PDB0_CH1DLY1 is 4003_6000h base + 44h offset = 4003_6044h
29
29
0
0
28
28
0
0
This read-only field is reserved and always has the value zero.
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
This read-only field is reserved and always has the value zero.
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
27
27
0
0
26
26
0
0
25
25
0
0
24
24
0
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
0
23
23
0
0
PDBx_CHnDLY0 field descriptions
PDBx_CHnDLY1 field descriptions
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
Chapter 35 Programmable Delay Block (PDB)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
DLY
DLY
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
775
0
0
0
0