MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 855

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 36 FlexTimer (FTM)
36.4.7 Center-Aligned PWM (CPWM) Mode
The center-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0),
(COMBINE = 0), and (CPWMS = 1).
The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the
period is determined by 2 × (MOD − CNTIN)(see the following figure). MOD must be
kept in the range of 0x0001 to 0x7FFF because values outside this range can produce
ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts
down until it reaches CNTIN.
The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (FTM counter = CnV) when the FTM counting is down (at the begin of the
pulse width) and when the FTM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of CNTIN.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
FTM counter = CNTIN
counter overflow
counter overflow
channel (n) match
channel (n) match
(FTM counting
(FTM counting
FTM counter =
FTM counter =
is up)
is down)
MOD
MOD
channel (n) output
pulse width
2 x (CnV - CNTIN)
period
2 x (MOD - CNTINCNTIN)
Figure 36-184. CPWM Period and Pulse Width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the FTM counter reaches the value in the CnV register,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up (see the following figure).
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
855