MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 288

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Introduction
No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention
mode and all debug operation can continue after waking from LLS, even in cases where
system wakeup is due to a system reset event.
Entering into a VLLS mode causes all the debug controls and settings to be powered off.
To give time to the debugger to sync with the MCU, the MDM AP Control Register
includes a Very Low Leakage Debug Request (VLLDBGREQ) bit that is set to configure
the Mode Controller logic to hold the system in reset after the next recovery from a
VLLS mode. This bit allows the debugger time to re-initialize the debug module before
the debug session continues.
The VLLDBGREQ bit clears automatically due to the reset generated as part of the
VLLS recovery.
The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge
(VLLDBGACK) bit that is set to release the ARM core being held in reset following a
VLLS recovery. The debugger re-initializes all debug IP and then asserts the
VLLDBGACK control bit to allow the Mode Controller to release the ARM core from
reset and allow CPU operation to begin.
The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears
automatically due to the reset generated as part of the next VLLS recovery.
13.1.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial
conditions.
When the ARM processor exits reset, it sets up the stack, program counter (PC), and link
register (LR).
The device resets can be generalized into three distinct groups: POR, system resets, and
debug resets.
POR reset:
System resets:
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• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF
• Power-on reset (POR)
• External pin reset (PIN)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.