MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 695

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting
conversion time is 57.625 µs (AverageNum). This results in a total conversion time of
1.844 ms.
31.4.5.6.3 Short conversion time configuration
A configuration for short ADC conversion is: 8-bit single ended mode with the bus clock
selected as the input clock source, the input clock divide-by-1 ratio selected, a bus
frequency of 20 MHz, long sample time disabled, and high speed conversion enabled.
The conversion time for this conversion is calculated by using
information provided in
variables of
The resulting conversion time is generated using the parameters listed in in the preceding
table. Therefore, for bus clock equal to 20 MHz and ADCK equal to 20 MHz, the
resulting conversion time is 1.45 µs.
31.4.5.7 Hardware average function
The hardware average function can be enabled (AVGE=1) to perform a hardware average
of multiple conversions. The number of conversions is determined by the AVGS[1:0]
bits, which select 4, 8, 16, or 32 conversions to be averaged. While the hardware average
function is in progress, the ADACT bit will be set.
Freescale Semiconductor, Inc.
AverageNum
HSCAdder
HSCAdder
SFCAdder
LSTAdder
Variable
Variable
BCT
Figure
31-95.
Table 31-113. Typical conversion time (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 31-107
Table 31-114. Typical conversion time
through
5 ADCK cycles + 5 bus clock cycles
Table
17 ADCK cycles
0 ADCK cycles
31-111. The table below list the
Time
Time
Chapter 31 Analog-to-Digital Converter (ADC)
0
1
2
Figure 31-95
and the
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