MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 407

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
4000_902C
4000_903C
4000_903E
4000_903E
4000_904C
4000_9028
4000_9028
4000_9028
4000_9030
4000_9034
4000_9036
4000_9036
4000_9038
4000_9040
4000_9044
4000_9046
4000_9048
4000_9048
4000_9048
4000_9050
Absolute
address
(hex)
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD1_NBYTES_MLNO)
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD1_NBYTES_MLOFFYES)
TCD Last Source Address Adjustment
(DMA_TCD1_SLAST)
TCD Destination Address (DMA_TCD1_DADDR)
TCD Signed Destination Address Offset
(DMA_TCD1_DOFF)
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD1_CITER_ELINKYES)
DMA_TCD1_CITER_ELINKNO
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD1_DLASTSGA)
TCD Control and Status (DMA_TCD1_CSR)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD1_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD1_BITER_ELINKNO)
TCD Source Address (DMA_TCD2_SADDR)
TCD Signed Source Address Offset (DMA_TCD2_SOFF)
TCD Transfer Attributes (DMA_TCD2_ATTR)
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD2_NBYTES_MLNO)
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD2_NBYTES_MLOFFYES)
TCD Last Source Address Adjustment
(DMA_TCD2_SLAST)
TCD Destination Address (DMA_TCD2_DADDR)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Register name
DMA memory map (continued)
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
(in bits)
Width
32
32
32
32
32
16
16
16
32
16
16
16
32
16
16
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Section/
21.3.20/
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21.3.25/
21.3.26/
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21.3.17/
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21.3.21/
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21.3.24/
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